In this course, students will learn about automated digital design. They will learn to utilize a hardware description language (HDL) in the digital design process. The language of choice is Verilog. Emphasis is on system level concepts and high-level design, and the language syntax will be presented to support the realization of the presented concepts. The students will get to design, synthesize (compile), simulate, and optimize the digital design, on a real hardware simulation platform. More specifically, a commercial computer aided design tool will be used to design a series of increasingly sophisticated designs on field programmable gate arrays (FPGAs).

  • Instructor: Prof. Farinaz Koushanfar, UCSD ECE
  • Time: Tues/Thurs 12:30-13:50PM
  • Location: Online
  • Office Hours: Thurs 2pm-4:00pm (in person and by email appointment)
  • Discussion: Piazza