Date Lecture Logistics
09/23/2021 Lecture #1: Introduction
[slides]

09/28/2021 Lecture #2: System Verilog
[slides]

09/30/2021 Lecture #3: ASIC, FPGA Architecture, Logic Synthesis
[slides]

10/05/2021 Lecture #4: Introduction to SystemVerilog (1)
[slides]

Homework_0
10/07/2021 Lecture #5: Introduction to SystemVerilog (2)
[slides]

10/12/2021 Lecture #6: Anatomy of SystemVerilog Module
[slides]

10/14/2021 Lecture #7: SystemVerilog Data Types, Continuous Assignment Statement and Conditional Operator
[slides]

Mini Project_1
10/19/2021 Lecture #8: Blocking and Non-blocking Assignments
[slides]

10/21/2021 Lecture #9: Procedural Blocks (1)
[slides]

Mini Project_2
10/26/2021 Lecture #10: Procedural Blocks (2)
[slides]

10/28/2021 Lecture #11: RTL Programming Statements
[slides]

11/02/2021 Lecture #12: RTL Programming Statements
[slides]

Mini Project_3
11/04/2021 Lecture #13: Finite State Machine (1)
[slides]

11/09/2021 Lecture #14: Finite State Machine (2)
[slides]

Final Project
11/16/2021 Lecture #15: Delay optimization
[slides]

11/18/2021 Lecture #16: Project discussions part 1
[slides]

11/23/2021 Lecture #17: Project discussions part 2
[slides]

11/25/2021 Lecture #18: Thanksgiving Holiday!

11/30/2021 Lecture #19: Project discussions part 3
[slides]

12/02/2021 Lecture #20: Final project presentation

12/09/2021 Final project report Due