Schedule
| Date | Lecture | Logistics | ||
|---|---|---|---|---|
| 09/23/2021 |
Lecture #1:
Introduction
[slides] |
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| 09/28/2021 |
Lecture #2:
System Verilog
[slides] |
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| 09/30/2021 |
Lecture #3:
ASIC, FPGA Architecture, Logic Synthesis
[slides] |
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| 10/05/2021 |
Lecture #4:
Introduction to SystemVerilog (1)
[slides] |
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| 10/07/2021 |
Lecture #5:
Introduction to SystemVerilog (2)
[slides] |
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| 10/12/2021 |
Lecture #6:
Anatomy of SystemVerilog Module
[slides] |
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| 10/14/2021 |
Lecture #7:
SystemVerilog Data Types, Continuous Assignment Statement and Conditional Operator
[slides] |
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| 10/19/2021 |
Lecture #8:
Blocking and Non-blocking Assignments
[slides] |
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| 10/21/2021 |
Lecture #9:
Procedural Blocks (1)
[slides] |
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| 10/26/2021 |
Lecture #10:
Procedural Blocks (2)
[slides] |
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| 10/28/2021 |
Lecture #11:
RTL Programming Statements
[slides] |
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| 11/02/2021 |
Lecture #12:
RTL Programming Statements
[slides] |
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| 11/04/2021 |
Lecture #13:
Finite State Machine (1)
[slides] |
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| 11/09/2021 |
Lecture #14:
Finite State Machine (2)
[slides] |
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| 11/16/2021 |
Lecture #15:
Delay optimization
[slides] |
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| 11/18/2021 |
Lecture #16:
Project discussions part 1
[slides] |
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| 11/23/2021 |
Lecture #17:
Project discussions part 2
[slides] |
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| 11/25/2021 |
Lecture #18:
Thanksgiving Holiday!
|
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| 11/30/2021 |
Lecture #19:
Project discussions part 3
[slides] |
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| 12/02/2021 |
Lecture #20:
Final project presentation
|
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| 12/09/2021 | Final project report Due | |||