ECE 111 Advanced Digital Design Project

Subject	Recodings
Subject #1: Introduction and Orientation	Set 0 Course logistics Set 1 Course Overview Set 2 Why this class Set 3 Career paths in VLSI design Set 4 Hardware description language (HDL) -- evolution and usage Set 5 Back to digital design basics Set 6 SystemVerilog Set 7 SystemVerilog hierarchical modeling concepts
Subject #2: Introduction to SystemVerilog	Set 1 Basics of Structural \& Behavioral Set 2 Basics of SystemVerilog module elements
Subject #3: FPGA	Set 1 Memory Arrays Set 1 Memory Arrays Example Set 2 Different Types of Memories Set 3 Logic with Memories Set 4 FPGA Set 5 FPGA & ASIC Digital Design Flow Set 6 Simulation and Synthesis
Subject #4 & #5: Combinational Logic in SystemVerilog	Set 1 SystemVerilog Modeling Abstractions (Behavioral, Data Flow and RTL) Set 2 SystemVerilog Modeling Abstractions (Gate Level and Switch Level) Set 3 Examples in Different Abstraction Levels Set 4 SystemVerilog Data Types Set 5 Conditional Operator and Continuous Assignment Statement
Subject #6: Delay Simulation, Flip Flops and Blocking vs non-Blocking	Set 1 Delay Simulation Set 2 Flip Flops Set 3 Blocking vs non-Blocking Assignment Set 4 Inter-Delay and Intra-Delay Set 5 More Examples
Subject #7: Finite State Machine in SystemVerilog	Set 1 Mealy and Moore Finite State Machine Set 2 FSM in SystemVerilog Set 3 Traffic Light FSM